1. Field of the Invention
The invention relates to a manufacturing method for a buried circuit structure, and more particularly, to a manufacturing method for a buried circuit structure applied with a selective metal chemical vapor deposition (MCVD).
2. Description of the Prior Art
Along with miniaturization and complexity of integrated circuit (IC), the prior art has always devoted itself to scale down the device size for fabricating enough devices and constructing efficient circuit within a limited chip surface. Therefore approaches such as buried bit lines, buried word lines, or multilevel-interconnect structures are developed to create and realize three-dimension IC architectures.
Please refer to FIGS. 1-3, which are cross-sectional views illustrating a conventional manufacturing method for buried bit lines. The prior art first provides a substrate 100 having devices (not shown) formed therein. Then, a plurality of trenches 104 is formed in the substrate 100 and followed by forming a contact window (not shown) in each trench 104. A first metal layer 108 serving as a buried bit line is subsequently formed in the trench 104. Then, the trenches 104 are filled by an insulating layer and followed by forming a patterned hard mask 102 on the substrate 100. The pattern hard mask 102 is formed to define a plurality of trenches 106 having an extension direction perpendicular to an extension direction of the trenches 104. After forming the trenches 106, an insulating layer 110 is formed to cover the first metal layer 108 exposed in a bottom of the trenches 106, and followed by forming a second metal layer 112 such as a tungsten layer in the trenches 106. Subsequently, a silicon oxide layer 114 is formed in the trenches 106 and on the substrate 100. As shown in FIG. 1, the silicon oxide layer 114 covers the second metal layer 112.
Please refer to FIG. 2 and FIG. 3. After forming the silicon oxide layer 114, an etching back process is performed to remove a portion of the silicon oxide layer 114 in the trenches 106 to form a silicon oxide spacer on sidewalls of each trench 106. The silicon oxide spacer 116 covers at least a portion of the second metal layer 112 for defining a position and thickness of the buried bit line formed afterwards. After forming the silicon oxide spacers 116, an etching process is performed to remove the second metal layer 112 not covered by the silicon oxide spacers 116, and thus a metal layer 118 is obtained on two opposite sidewalls of the trenches 106, respectively. The metal layer 118 serves as a buried bit line, respectively. Thereafter, a protecting layer (not shown) is formed in the trenches 106 for filling the trenches 106 and the fabrications of the buried word lines and the buried bit lines are accomplished.
Please still refer to FIG. 2. It is noteworthy that the second metal layer 112 is a layer having a substantial thickness; therefore it is difficult to perform the etching process to remove the second metal layer 112 precisely. In the case that the second metal layer 112 is not etched completely, the final metal layers 118 as shown in FIG. 3 may contact each other at the bottom of the trench 106. Accordingly, buried bit line short circuit is occurred. On the contrary, in the case that the second metal layer 112 is over-etched, the final metal layers 118 as shown in FIG. 3 are undesirably and excessively thinned down. Accordingly, resistance is increased and thus performance of the IC is deteriorated.
Therefore, the approach that utilizing the silicon oxide spacer 116 define the position and the thickness of the buried bit lines have suffered some disadvantages of complicating process and difficulty with the process control. Thus, a simplified and economized manufacturing method for a buried circuit structure that is able to precisely form the buried circuit structure in the predetermined position is still in need.